用于人工神经网络计算的VLIW/SIMD微处理器

[1992] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1992-08-04 DOI:10.1109/ASAP.1992.218573

K. Asanović, J. Beck, Brian E. D. Kingsbury, P. Kohn, N. Morgan, J. Wawrzynek

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引用次数: 15

摘要

SPERT (synthetic perceptron testbed)是一种完全可编程的单芯片微处理器，旨在有效地执行人工神经网络算法。第一个实现采用1.2 μ m CMOS技术，时钟频率为50 MHz，并且正在设计一个原型系统，用于占用Sun Sparcstation内的双SBus插槽。在模式分类期间，SPERT维持每秒超过300*10/sup 6/连接，在运行流行的误差反向传播训练算法时，每秒约100*10/sup 6/连接更新。对于感兴趣的算法，这表示比Sparcstation-2的速度提高了大约两个数量级。该集团生产的早期系统环形阵列处理器(RAP)使用商用DSP芯片。与具有类似性能的RAP多处理器相比，SPERT在满足不动点算法的情况下，将问题的成本降低了一个数量级以上

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SPERT: a VLIW/SIMD microprocessor for artificial neural network computations

SPERT (synthetic perceptron testbed) is a fully programmable single chip microprocessor designed for efficient execution of artificial neural network algorithms. The first implementation is in a 1.2 mu m CMOS technology with a 50 MHz clock rate, and a prototype system is being designed to occupy a double SBus slot within a Sun Sparcstation. SPERT sustains over 300*10/sup 6/ connections per second during pattern classification, and around 100*10/sup 6/ connection updates per second while running the popular error backpropagation training algorithm. This represents a speedup of around two orders of magnitude over a Sparcstation-2 for algorithms of interest. An earlier system produced by the group, the Ring Array Processor (RAP), used commercial DSP chips. Compared with a RAP multiprocessor of similar performance, SPERT represents over an order of magnitude reduction in cost for problems where fixed-point arithmetic is satisfactory.<>

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[1992] Proceedings of the International Conference on Application Specific Array Processors

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