Ultra-low-power analog and digital circuits and microsystems using disruptive ultra-low-leakage design techniques

In this paper, we describe circuits and microsystems applications of a disruptive ultra-low-leakage design technique for drastically reducing the off current in CMOS analog and digital functions without reducing the functional performance. The technique uses a pair of source-connected n- and p-MOSFETs, implementing an auto-bias of the stand-by gate-to-source voltage of the nMOS transistor at a negative voltage and that of the p-device at a positive level, thereby reducing the off current towards its physical limits. Changing the gate and drain connections, we propose a series of ultra-low-power basic blocks : a 2-terminal diode, a 3-terminal transistor and a voltage follower. These blocks can be combined to yield a 7-transistor SRAM cell and an MTCMOS latch with record low stand-by leakage but still high-speed performance, as well as high-efficiency power-management units for RF and PV energy harvesting and a microwatt interface for implanted capacitive sensors.