C. Shung, R. Jain, K. Rimey, Edward Wang, M. Srivastava, B. Richards, E. Lettang, S. K. Azim, L. Thon, P. Hilfinger, J. Rabaey, R. Brodersen
{"title":"一个集成的CAD系统,用于特定算法的IC设计","authors":"C. Shung, R. Jain, K. Rimey, Edward Wang, M. Srivastava, B. Richards, E. Lettang, S. K. Azim, L. Thon, P. Hilfinger, J. Rabaey, R. Brodersen","doi":"10.1109/HICSS.1989.47146","DOIUrl":null,"url":null,"abstract":"Lager, an integrated CAD (computer-aided design) system for algorithm-specific IC design, is described. It consists of a behavioral mapper and a silicon assembler. To generate a chip from a behavioral description, the user specifies both the behavioral description and a parameterized structural description. The behavior is mapped onto the parameterized structure to produce microcode and parameter values. The silicon assembler then translates the fill-out structural description into a physical layout. A number of algorithm-specific ICs designed with Lager have been fabricated and tested. A robot-control chip is described.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"115","resultStr":"{\"title\":\"An integrated CAD system for algorithm-specific IC design\",\"authors\":\"C. Shung, R. Jain, K. Rimey, Edward Wang, M. Srivastava, B. Richards, E. Lettang, S. K. Azim, L. Thon, P. Hilfinger, J. Rabaey, R. Brodersen\",\"doi\":\"10.1109/HICSS.1989.47146\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Lager, an integrated CAD (computer-aided design) system for algorithm-specific IC design, is described. It consists of a behavioral mapper and a silicon assembler. To generate a chip from a behavioral description, the user specifies both the behavioral description and a parameterized structural description. The behavior is mapped onto the parameterized structure to produce microcode and parameter values. The silicon assembler then translates the fill-out structural description into a physical layout. A number of algorithm-specific ICs designed with Lager have been fabricated and tested. A robot-control chip is described.<<ETX>>\",\"PeriodicalId\":300182,\"journal\":{\"name\":\"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-01-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"115\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/HICSS.1989.47146\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/HICSS.1989.47146","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An integrated CAD system for algorithm-specific IC design
Lager, an integrated CAD (computer-aided design) system for algorithm-specific IC design, is described. It consists of a behavioral mapper and a silicon assembler. To generate a chip from a behavioral description, the user specifies both the behavioral description and a parameterized structural description. The behavior is mapped onto the parameterized structure to produce microcode and parameter values. The silicon assembler then translates the fill-out structural description into a physical layout. A number of algorithm-specific ICs designed with Lager have been fabricated and tested. A robot-control chip is described.<>