内存BIST的可配置架构

2011 9th East-West Design & Test Symposium (EWDTS) Pub Date : 2011-09-09 DOI:10.1109/EWDTS.2011.6116571

A. Lotfi, P. Kabiri, Z. Navabi

{"title":"内存BIST的可配置架构","authors":"A. Lotfi, P. Kabiri, Z. Navabi","doi":"10.1109/EWDTS.2011.6116571","DOIUrl":null,"url":null,"abstract":"The number of memory components in today's chips is increasing considerably. Through the limitations on area and number of test pins, it is not feasible to use a separate BIST architecture for testing every memory on the chip. Therefore, it is essential to have a configurable BIST architecture. In this paper, a configurable memory BIST architecture that can test different memories having different sizes and configurations with an arbitrary test algorithm is proposed.","PeriodicalId":339676,"journal":{"name":"2011 9th East-West Design & Test Symposium (EWDTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Configurable architecture for memory BIST\",\"authors\":\"A. Lotfi, P. Kabiri, Z. Navabi\",\"doi\":\"10.1109/EWDTS.2011.6116571\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The number of memory components in today's chips is increasing considerably. Through the limitations on area and number of test pins, it is not feasible to use a separate BIST architecture for testing every memory on the chip. Therefore, it is essential to have a configurable BIST architecture. In this paper, a configurable memory BIST architecture that can test different memories having different sizes and configurations with an arbitrary test algorithm is proposed.\",\"PeriodicalId\":339676,\"journal\":{\"name\":\"2011 9th East-West Design & Test Symposium (EWDTS)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-09-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 9th East-West Design & Test Symposium (EWDTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EWDTS.2011.6116571\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 9th East-West Design & Test Symposium (EWDTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2011.6116571","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

在今天的芯片中，内存组件的数量正在显著增加。由于测试引脚的面积和数量的限制，使用单独的BIST架构来测试芯片上的每个存储器是不可行的。因此，拥有一个可配置的BIST体系结构是必不可少的。本文提出了一种可配置内存BIST体系结构，该体系结构可以用任意的测试算法测试不同大小和配置的内存。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Configurable architecture for memory BIST

The number of memory components in today's chips is increasing considerably. Through the limitations on area and number of test pins, it is not feasible to use a separate BIST architecture for testing every memory on the chip. Therefore, it is essential to have a configurable BIST architecture. In this paper, a configurable memory BIST architecture that can test different memories having different sizes and configurations with an arbitrary test algorithm is proposed.

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2011 9th East-West Design & Test Symposium (EWDTS)

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