Ultrafine grain FPGAs with polarity controllable transistors

In the quest to push further the Moore's scaling laws, intensive development efforts have been invested on seeking for alternatives to planar CMOS transistors at advanced technology nodes. In particular, recent years have witnessed the massive commercialization of the fin-basedfield effect transistors (FinFETs) at the 10, 14 and 22-nm technology nodes [1-3]. In addition to FinFET technology, several devices are currently investigated by following the trend toward 1D structures. Among them, carbon nanotubes FETs [4] and vertically stacked silicon nanowires FETs (SiNWFETs) [5] are promising extensions to current tri-gate FinFETs technology, which exploit the 1-D properties of their channels to exhibit superior performances. Moreover, these novel transistor technologies employ the gate-all-around (GAA) structure which can improve the electrostatic control of the channel, leading to a higher ION/IOFF ratio and reduced leakage current [6]. More than the performance improvement, these novel transistor technologies present another possible direction in pushing the Moore's scaling laws: functionality enhanced device. Especially at advanced technology nodes, transistors are strongly affected by Schottky contacts at the source and drain interfaces. As a result, transistors may operate with an ambipolar behavior, i.e., the device can exhibit nand p-type characteristics simultaneously. Indeed, to achieve pure n- and p-type polarity, the ambipolar behavior of the devices is typically suppressed through additional process steps. However, new design methodologies [7-9] have shown attractive opportunities in controlling the ambipolar phenomenon through programmable polarity devices. By engineering the source and drain contacts and by constructing independent doublegate structures, the device polarity can be electrostatically programmed to be either nor p-type. Such functionality-enhanced devices have been demonstrated using silicon [10,11] and carbon electronics [12,13]. In this chapter, we focus on a double-gate SiNWFET (DG-SiNWFET), built using a top-down fabrication flow [14].