网络芯片的可重构设计

2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum Pub Date : 2012-05-21 DOI:10.1109/IPDPSW.2012.35

Tao Li, Zhentao Liu, Huimin Du, Lei Zhang, Jungang Han, Lin Jiang, Qingang Dong

{"title":"网络芯片的可重构设计","authors":"Tao Li, Zhentao Liu, Huimin Du, Lei Zhang, Jungang Han, Lin Jiang, Qingang Dong","doi":"10.1109/IPDPSW.2012.35","DOIUrl":null,"url":null,"abstract":"This paper presents a reconfigurable architecture and associated design methodology for developing networking silicon chips. The tools include most of the common traffic QoS features and low level interfaces as well as some special features for extensible design. When coupled with the design tools, this architecture provides powerful capabilities for the design of highly flexible networking silicon IP cores.","PeriodicalId":378335,"journal":{"name":"2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum","volume":"15 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Reconfigurable Designs for Networking Silicon\",\"authors\":\"Tao Li, Zhentao Liu, Huimin Du, Lei Zhang, Jungang Han, Lin Jiang, Qingang Dong\",\"doi\":\"10.1109/IPDPSW.2012.35\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a reconfigurable architecture and associated design methodology for developing networking silicon chips. The tools include most of the common traffic QoS features and low level interfaces as well as some special features for extensible design. When coupled with the design tools, this architecture provides powerful capabilities for the design of highly flexible networking silicon IP cores.\",\"PeriodicalId\":378335,\"journal\":{\"name\":\"2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum\",\"volume\":\"15 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-05-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPDPSW.2012.35\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPDPSW.2012.35","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文提出了一种可重构的网络硅芯片体系结构和相关的设计方法。这些工具包括大多数常见的流量QoS特性和低级接口，以及一些用于可扩展设计的特殊特性。当与设计工具相结合时，该架构为设计高度灵活的网络硅IP核提供了强大的功能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Reconfigurable Designs for Networking Silicon

This paper presents a reconfigurable architecture and associated design methodology for developing networking silicon chips. The tools include most of the common traffic QoS features and low level interfaces as well as some special features for extensible design. When coupled with the design tools, this architecture provides powerful capabilities for the design of highly flexible networking silicon IP cores.

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2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum

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