3D异构多核处理器的基本原理

2013 IEEE 31st International Conference on Computer Design (ICCD) Pub Date : 2013-11-07 DOI:10.1109/ICCD.2013.6657038

E. Rotenberg, Brandon H. Dwiel, E. Forbes, Zhenqian Zhang, Randy Widialaksono, Rangeen Basu Roy Chowdhury, Nyunyi M. Tshibangu, S. Lipa, W. R. Davis, P. Franzon

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引用次数: 20

摘要

单isa异构多核处理器由功能相同但微体系结构不同的多个核心类型组成。这种模式作为一种优化性能和能源的方式已经获得了很多关注。当当前执行的程序的指令级行为变化时，它被迁移到该行为的最有效的核心类型。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Rationale for a 3D heterogeneous multi-core processor

Single-ISA heterogeneous multi-core processors are comprised of multiple core types that are functionally equivalent but microarchitecturally diverse. This paradigm has gained a lot of attention as a way to optimize performance and energy. As the instruction-level behavior of the currently executing program varies, it is migrated to the most efficient core type for that behavior.

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2013 IEEE 31st International Conference on Computer Design (ICCD)

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