{"title":"基于MIPS指令提取模块的32位RISC CPU设计","authors":"Kui Yi, YueHua Ding","doi":"10.1109/JCAI.2009.158","DOIUrl":null,"url":null,"abstract":"In this paper, we analyze MIPS instruction format¿ instruction data path¿decoder module function and design theory basend on RISC CPUT instruction set. Furthermore, we design instruction fetch(IF) module of 32-bit CPU based on RISC CPU instruction set. Function of IF module mainly includes fetch instruction and latch module¿address arithmetic module¿ check validity of instruction module¿synchronous control module. Function of IF modules are implemented by pipeline and simulated successfully on QuartusII¿","PeriodicalId":154425,"journal":{"name":"2009 International Joint Conference on Artificial Intelligence","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"32-bit RISC CPU Based on MIPS Instruction Fetch Module Design\",\"authors\":\"Kui Yi, YueHua Ding\",\"doi\":\"10.1109/JCAI.2009.158\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we analyze MIPS instruction format¿ instruction data path¿decoder module function and design theory basend on RISC CPUT instruction set. Furthermore, we design instruction fetch(IF) module of 32-bit CPU based on RISC CPU instruction set. Function of IF module mainly includes fetch instruction and latch module¿address arithmetic module¿ check validity of instruction module¿synchronous control module. Function of IF modules are implemented by pipeline and simulated successfully on QuartusII¿\",\"PeriodicalId\":154425,\"journal\":{\"name\":\"2009 International Joint Conference on Artificial Intelligence\",\"volume\":\"67 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Joint Conference on Artificial Intelligence\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/JCAI.2009.158\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Joint Conference on Artificial Intelligence","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/JCAI.2009.158","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
32-bit RISC CPU Based on MIPS Instruction Fetch Module Design
In this paper, we analyze MIPS instruction format¿ instruction data path¿decoder module function and design theory basend on RISC CPUT instruction set. Furthermore, we design instruction fetch(IF) module of 32-bit CPU based on RISC CPU instruction set. Function of IF module mainly includes fetch instruction and latch module¿address arithmetic module¿ check validity of instruction module¿synchronous control module. Function of IF modules are implemented by pipeline and simulated successfully on QuartusII¿
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
