整数多精度算法协处理器在Zynq Ultrascale+ MPSoC上的实现

2021 28th International Conference on Mixed Design of Integrated Circuits and System Pub Date : 2021-06-24 DOI:10.23919/MIXDES52406.2021.9497554

T. Stefański, K. Rudnicki, Wojciech Zebrowski

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引用次数: 0

摘要

最近，我们公开了多精度算术协处理器(MPA)的源代码。本文介绍了该MPA协处理器在现代Zynq Ultrascale+片上多处理器系统上的实现和基准测试结果，该系统结合了现场可编程门阵列和四核ARM Cortex-A53 64位中央处理器(CPU)。在我们的基准测试中，单个协处理器可以比使用软件库模拟MPA的同一芯片中的单个CPU核心快4.5倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Implementation of Coprocessor for Integer Multiple Precision Arithmetic on Zynq Ultrascale+ MPSoC

Recently, we have opened the source code of coprocessor for multiple-precision arithmetic (MPA). In this contribution, the implementation and benchmarking results for this MPA coprocessor are presented on modern Zynq Ultrascale+ multiprocessor system on chip, which combines field-programmable gate array with quad-core ARM Cortex-A53 64-bit central processing unit (CPU). In our benchmark, a single coprocessor can be up to 4.5 times faster than a single CPU core within the same chip emulating MPA using a software library.

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2021 28th International Conference on Mixed Design of Integrated Circuits and System

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