一种高性能微处理器电桥模式的实验评估

23rd IEEE VLSI Test Symposium (VTS'05) Pub Date : 2005-05-01 DOI:10.1109/VTS.2005.44

S. Chakravarty, Yi-Shing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, C. Prunty, Eric W. Savage, Rehan Sheikh, Eric N. Tran, Khen Wee

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引用次数: 13

摘要

介绍了一种高性能微处理器针对真实桥的扫描模式的硅评估。证明了生成真实桥型的实用性。硅数据，有和没有功能故障，并在存在n检测测试提出。数据指出了桥梁模式的价值和效率。数据还显示，与补充卡在模式相比，使用补充桥接模式具有优势。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Experimental evaluation of bridge patterns for a high performance microprocessor

Silicon evaluation of scan patterns, targeting realistic bridges, for a high performance microprocessor is presented. The practicality of generating realistic bridge patterns is demonstrated. Silicon data, with and without functional fails, and in the presence of n-detect tests are presented. Data points to the value of and efficiency of bridge patterns. Data also shows the advantage of using supplemental bridge patterns when compared with supplemental stuck-at patterns.

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23rd IEEE VLSI Test Symposium (VTS'05)

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