691 Mbps 1.392mm2可配置基数-16 turbo解码器ASIC在65nm CMOS 3GPP-LTE和WiMAX系统

2013 IEEE Asian Solid-State Circuits Conference (A-SSCC) Pub Date : 2013-12-23 DOI:10.1109/ASSCC.2013.6691006

Xubin Chen, Yun Chen, Yi Li, Yuebin Huang, Xiaoyang Zeng

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引用次数: 9

摘要

本文提出了一种用于3GPP-LTE和WiMAX系统的统一并行基数-16 turbo解码器ASIC。提出了一种二进制和双二进制turbo码的基数16译码方法，以降低编码复杂度和关键路径延迟。此外，标准中的两种不同的交织器采用低复杂度的地址生成器和桶移位网络实现。此外，四行内存分区使得并行的基数16解码没有地址冲突。ASIC采用台积电65nm CMOS工艺制造，在512MHz和5.5迭代下实现了691Mbps的吞吐量。对于326.4Mbps的LTE峰值数据速率，它在0.9V电源电压下仅消耗193mW，能量效率达到了前所未有的0.108nJ/bit/迭代。

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A 691 Mbps 1.392mm2 configurable radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems in 65nm CMOS

This paper presents a unified parallel radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems. A radix-16 decoding for both binary and duo-binary turbo codes is proposed to reduce complexity as well as critical path delay. In addition, the two distinct interleavers in the standards are implemented with low-complexity address generator and barrel shift networks. Furthermore, quad-bank memory partition facilitates parallel radix-16 decoding without address conflict. Fabricated in TSMC 65nm CMOS process, the ASIC attains 691Mbps throughput running at 512MHz and 5.5 iterations. For the 326.4Mbps LTE peak data rate, it consumes only 193mW at 0.9V supply voltage with unprecedented energy efficiency of 0.108nJ/bit/iteration.

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2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)

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