具有耦合匹配结构的v波段低噪声放大器

Yen-Chung Chiang, Yu-Chin Lin
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引用次数: 6

摘要

本文介绍了一种专为v波段应用而设计的三级低噪声放大器。所提出的LNA的每个阶段都是具有最小化噪声系数(NF)的电感退化的共源拓扑结构。栅极和源端电感形成耦合结构,以低NF电平扩展带宽。该LNA采用90纳米CMOS工艺技术实现,峰值增益为16.48 dB,最小NF为4.5 dB,输入PidB为-18.7 dBm。该LNA的功耗为17.47 mW,电源电压为1.2 v。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A low noise amplifier with coupled matching structure for V-band applications
In this paper, a three-stage low-noise amplifier (LNA) designed for V-band applications is presented. Each stage of the proposed LNA is the common-source topology with inductive degeneration for minimizing the noise figure (NF). The inductors at the gate and source terminals form a coupling structure which extends the bandwidth with a low NF level. This proposed LNA is implemented in the 90-nm CMOS process technology, which achieves a peak gain of 16.48 dB, a minimum NF of 4.5 dB, and an input PidB of -18.7 dBm. The proposed LNA consumes 17.47 mW power from a 1.2-V voltage supply.
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