Review on Low-Power Consumption Techniques for FPGA-based designs in IoT technology

This paper aims to give an overview and discuss power consumption techniques for FPGA-based designs, which will provide the necessary information about the low-power techniques and will give a new approach to the design optimisations that help to guide researchers in this field. The new emerging technologies such as IoT is evolving rapidly and one of the main concerns is power consumption. Nowadays, mobile devices are smart and perform difficult tasks including computations and control, which are being designed using FPGA, IP (hard and soft cores) and SoC. The necessity for developing low-power techniques will help mobile devices to process data during communication. It is obvious that FPGAs have many advantages compared to other digital integrated circuits but has one major disadvantage because they consume much power due to their complex architecture. Most of the low-power techniques for FPGAs focus on system-level and device-level (architecture) designs. In the end, conclusions will be given based on the analysis of low-power techniques.