90nm Cu / PECVD低k技术的芯片-封装相互作用

Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729) Pub Date : 2004-06-07 DOI:10.1109/IITC.2004.1345706

W. Landers, D. Edelstein, L. Clevenger, C. Das, C. Yang, T. Aoki, F. Beaulieu, J. Casey, A. Cowley, M. Cullinan, T. Daubenspeck, C. Davis, J. Demarest, É. Duchesne, L. Guerin, D. Hawken, T. Ivers, M. Lane, X. Liu, T. Lombardi, C. McCarthy, C. Muzzy, J. Nadeau-Filteau, D. Questad, W. Sauter, T. Shaw, J. Wright

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引用次数: 25

摘要

本文将对90nm PECVD低k技术的芯片-封装相互作用(CPI)评估进行综述。本文将介绍一种90nm技术，该技术使用Cu双damascene互连与SiCOH (K /spl sim/ 3.0) CVD BEOL绝缘体堆栈，跨越多种线键封装类型和倒装C4陶瓷和有机封装。通过使用IBM内部设计的SiCOH BEOL绝缘体，CPI不再是该技术节点的问题。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Chip-to-package interaction for a 90 nm Cu / PECVD low-k technology

A summary of chip-to-package interaction (CPI) evaluations for a 90 nm PECVD low k technology will be discussed. This review will cover a 90 nm technology that uses Cu dual damascene interconnections with a SiCOH (K /spl sim/ 3.0) CVD BEOL insulator stack across multiple wirebond package types and flipchip C4 ceramic and organic packages. It will be shown that with the use of IBM's internally engineered SiCOH BEOL insulator, CPI is not an issue with this technology node.

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Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729)

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