基于低密度奇偶校验码的8位逻辑ALU解码器的实现

2017 8th Annual Industrial Automation and Electromechanical Engineering Conference (IEMECON) Pub Date : 2017-08-01 DOI:10.1109/IEMECON.2017.8079598

Dibyendu Deogharia, Jayanta Bhattacharya, Sutapa Ray, Sulagno Roy, Swetaki Chatterjee, Abhishek Lahiri, Debarpita Ray, Arindam Nandi, Sunetra Bhattacharyya, Ranjan Kumar Kush, Y. Prakash

{"title":"基于低密度奇偶校验码的8位逻辑ALU解码器的实现","authors":"Dibyendu Deogharia, Jayanta Bhattacharya, Sutapa Ray, Sulagno Roy, Swetaki Chatterjee, Abhishek Lahiri, Debarpita Ray, Arindam Nandi, Sunetra Bhattacharyya, Ranjan Kumar Kush, Y. Prakash","doi":"10.1109/IEMECON.2017.8079598","DOIUrl":null,"url":null,"abstract":"A Decoder working on the logic of LDPC is designed for a 8 bit Logical ALU. The Simulation has been done to minimize the Voltage Leakage and Maximum throughput.","PeriodicalId":231330,"journal":{"name":"2017 8th Annual Industrial Automation and Electromechanical Engineering Conference (IEMECON)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Implementation of a decoder based on low-density parity-check code for 8 bit logical ALU\",\"authors\":\"Dibyendu Deogharia, Jayanta Bhattacharya, Sutapa Ray, Sulagno Roy, Swetaki Chatterjee, Abhishek Lahiri, Debarpita Ray, Arindam Nandi, Sunetra Bhattacharyya, Ranjan Kumar Kush, Y. Prakash\",\"doi\":\"10.1109/IEMECON.2017.8079598\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A Decoder working on the logic of LDPC is designed for a 8 bit Logical ALU. The Simulation has been done to minimize the Voltage Leakage and Maximum throughput.\",\"PeriodicalId\":231330,\"journal\":{\"name\":\"2017 8th Annual Industrial Automation and Electromechanical Engineering Conference (IEMECON)\",\"volume\":\"101 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 8th Annual Industrial Automation and Electromechanical Engineering Conference (IEMECON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEMECON.2017.8079598\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 8th Annual Industrial Automation and Electromechanical Engineering Conference (IEMECON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMECON.2017.8079598","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

针对8位逻辑ALU设计了一种基于LDPC逻辑的解码器。仿真已经完成，以尽量减少漏电压和最大吞吐量。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Implementation of a decoder based on low-density parity-check code for 8 bit logical ALU

A Decoder working on the logic of LDPC is designed for a 8 bit Logical ALU. The Simulation has been done to minimize the Voltage Leakage and Maximum throughput.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2017 8th Annual Industrial Automation and Electromechanical Engineering Conference (IEMECON)

自引率

0.00%

发文量