Investigation of Dielectric Pocket and Work function Engineering in Triple Material Hetero Gate Stack Oxide Double Gate TFET for Low Power Applications

The impact of dielectric pockets (DiP) in the drain and source side in the triple material double gate Tunnel FET along with hetero-gate stack oxide is demonstrated using Sentaurus TCAD simulations. The proposed device structure introduces the optimized DiPs at the source-channel (SP) and drain-channel (DP) junctions. The hetero gate stacked oxide improves the coupling between the gate and the channel and improves the ON current and subthreshold swing (SS). The presence of high-k DiP (Hf02) at the DP magnifies the depleted layer under the DP; as a result, the tunneling width (WTunneling) at the drain-side amplifies, and there is a remarkable decline in the ambipolar conduction. The presence of the low-k DiP (SiO2) at SP reduces the WTunneling at the source-side, improving the driving current of the device as the tunneling probability of charge particles increases at the source-side. By introducing the DiPs, there is an enhancement in the device's performance over conventional TFET in terms of lower SS, OFF-current (IOFF), and DIBL, higher ON-current (ION), and transconductance, and suppressed leakage current and improved ION/IOFF ratio. The DC characteristics and AC/RF parameter results illustrate that the device proposed is appropriate for applications of low power and high frequency