22.8 24- 35gb /s x4 VCSEL驱动IC,多速率无参考CDR, 0.13um SiGe BiCMOS

Y. Tsunoda, T. Shibasaki, S. Ide, Toshihiko Mori, Y. Koyanagi, Kazuhiro Tanaka, T. Ishihara, H. Tamura
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引用次数: 4

摘要

光互连技术由于光信号具有高带宽、低串扰的特性,是实现高速高密度互连的一种很有前途的解决方案。光互连的下一个挑战是移动到25Gb/s或更高的串行数据速率[1,2]。为了在带宽需求上实现灵活的互联,话单需要在宽调谐范围内以多种速率运行。一个可选择的多vco结构是克服这个问题的一种方法。然而,当在每个信道中分配多个vco时,由于vco的尺寸过大,使得高密度光链路难以实现。在本文中,我们提出了双环混合CDR,包括用于相位跟踪的相位插值器(PI)环路和位于通道区域外用于频率采集的通用VCO环路。我们开发了一种象限开关模拟pll环,能够跟踪与全速率频率对应的频率失配,最高可达35Gb/s。该双环混合CDR的4通道驱动IC采用0.13μm SiGe BiCMOS技术制造。利用这些电路,我们实现了一个多速率的驱动IC,范围从24到35Gb/s,用于灵活的光互连的无参考CDR。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS
The optical interconnect technologies are a promising solution for high-speed and high-density interconnects because of the high-bandwidth and low-crosstalk properties of optical signals. The next challenge for optical interconnects is to move to a serial data-rate of 25Gb/s or higher [1,2]. To achieve flexible interconnects on a bandwidth demand, a CDR is required to operate at multiple rates in a wide tuning range. A selectable multi-VCO structure is one method to overcome this issue. However, when multi-VCOs are allocated in each channel, the large size of VCOs makes it difficult to achieve a high-density optical link. In this paper, we presenta dual-loop hybrid CDR including a phase interpolator (PI) loop for phase tracking and a common VCO loop situated outside the channel areas for frequency acquisition. We develop a quadrant-switching analog Pl-loop that has the ability to track the frequency mismatch corresponding to full-rate frequency up to 35Gb/s. The 4-channel driver IC with this dual-loop hybrid CDR is fabricated in 0.13μm SiGe BiCMOS technology. With these circuits, we achieve a driver IC with a multi-rate, ranging from 24 to 35Gb/s, reference-less CDR for flexible optical interconnects.
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