Y. Tsunoda, T. Shibasaki, S. Ide, Toshihiko Mori, Y. Koyanagi, Kazuhiro Tanaka, T. Ishihara, H. Tamura
{"title":"22.8 24- 35gb /s x4 VCSEL驱动IC,多速率无参考CDR, 0.13um SiGe BiCMOS","authors":"Y. Tsunoda, T. Shibasaki, S. Ide, Toshihiko Mori, Y. Koyanagi, Kazuhiro Tanaka, T. Ishihara, H. Tamura","doi":"10.1109/ISSCC.2015.7063102","DOIUrl":null,"url":null,"abstract":"The optical interconnect technologies are a promising solution for high-speed and high-density interconnects because of the high-bandwidth and low-crosstalk properties of optical signals. The next challenge for optical interconnects is to move to a serial data-rate of 25Gb/s or higher [1,2]. To achieve flexible interconnects on a bandwidth demand, a CDR is required to operate at multiple rates in a wide tuning range. A selectable multi-VCO structure is one method to overcome this issue. However, when multi-VCOs are allocated in each channel, the large size of VCOs makes it difficult to achieve a high-density optical link. In this paper, we presenta dual-loop hybrid CDR including a phase interpolator (PI) loop for phase tracking and a common VCO loop situated outside the channel areas for frequency acquisition. We develop a quadrant-switching analog Pl-loop that has the ability to track the frequency mismatch corresponding to full-rate frequency up to 35Gb/s. The 4-channel driver IC with this dual-loop hybrid CDR is fabricated in 0.13μm SiGe BiCMOS technology. With these circuits, we achieve a driver IC with a multi-rate, ranging from 24 to 35Gb/s, reference-less CDR for flexible optical interconnects.","PeriodicalId":188403,"journal":{"name":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS\",\"authors\":\"Y. Tsunoda, T. Shibasaki, S. Ide, Toshihiko Mori, Y. Koyanagi, Kazuhiro Tanaka, T. Ishihara, H. Tamura\",\"doi\":\"10.1109/ISSCC.2015.7063102\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The optical interconnect technologies are a promising solution for high-speed and high-density interconnects because of the high-bandwidth and low-crosstalk properties of optical signals. The next challenge for optical interconnects is to move to a serial data-rate of 25Gb/s or higher [1,2]. To achieve flexible interconnects on a bandwidth demand, a CDR is required to operate at multiple rates in a wide tuning range. A selectable multi-VCO structure is one method to overcome this issue. However, when multi-VCOs are allocated in each channel, the large size of VCOs makes it difficult to achieve a high-density optical link. In this paper, we presenta dual-loop hybrid CDR including a phase interpolator (PI) loop for phase tracking and a common VCO loop situated outside the channel areas for frequency acquisition. We develop a quadrant-switching analog Pl-loop that has the ability to track the frequency mismatch corresponding to full-rate frequency up to 35Gb/s. The 4-channel driver IC with this dual-loop hybrid CDR is fabricated in 0.13μm SiGe BiCMOS technology. With these circuits, we achieve a driver IC with a multi-rate, ranging from 24 to 35Gb/s, reference-less CDR for flexible optical interconnects.\",\"PeriodicalId\":188403,\"journal\":{\"name\":\"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-03-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2015.7063102\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2015.7063102","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS
The optical interconnect technologies are a promising solution for high-speed and high-density interconnects because of the high-bandwidth and low-crosstalk properties of optical signals. The next challenge for optical interconnects is to move to a serial data-rate of 25Gb/s or higher [1,2]. To achieve flexible interconnects on a bandwidth demand, a CDR is required to operate at multiple rates in a wide tuning range. A selectable multi-VCO structure is one method to overcome this issue. However, when multi-VCOs are allocated in each channel, the large size of VCOs makes it difficult to achieve a high-density optical link. In this paper, we presenta dual-loop hybrid CDR including a phase interpolator (PI) loop for phase tracking and a common VCO loop situated outside the channel areas for frequency acquisition. We develop a quadrant-switching analog Pl-loop that has the ability to track the frequency mismatch corresponding to full-rate frequency up to 35Gb/s. The 4-channel driver IC with this dual-loop hybrid CDR is fabricated in 0.13μm SiGe BiCMOS technology. With these circuits, we achieve a driver IC with a multi-rate, ranging from 24 to 35Gb/s, reference-less CDR for flexible optical interconnects.