T. Iwamoto, T. Ogura, M. Terai, H. Watanabe, N. Ikarashi, M. Miyamura, T. Tatsumi, M. Saitoh, A. Morioka, K. Watanabe, Y. Saito, Y. Yabe, T. Ikarashi, K. Masuzaki, Y. Mochizuki, T. Mogami
{"title":"具有双多晶硅栅极的高制造低功率和高速HfSiO CMOS场效应管","authors":"T. Iwamoto, T. Ogura, M. Terai, H. Watanabe, N. Ikarashi, M. Miyamura, T. Tatsumi, M. Saitoh, A. Morioka, K. Watanabe, Y. Saito, Y. Yabe, T. Ikarashi, K. Masuzaki, Y. Mochizuki, T. Mogami","doi":"10.1109/IEDM.2003.1269362","DOIUrl":null,"url":null,"abstract":"For 90 nm node poly-Si gated MISFETs with HfSiO (1.8 nm) insulator, a nearly symmetrical set of Vths for NFET and PFET: (0.38 V and -0.46 V, respectively) have been realized for low power device operation. The key technology is the suppression of Vth instability in PFETs arising from oxidation of the poly-Si/HfSiO interface, combined with channel engineering for the PFET. Our poly-Si/HfSiO gate-stacked CMOSFETs realize low I/sub off/ (N/PFET: 4.8/3.6 pA//spl mu/m) and high I/sub on/ (N/PFET: 469/140 /spl mu/A//spl mu/m) at V/sub DD/=1.2 V. Further, for SRAM cell using this CMOS, normal operation has been achieved.","PeriodicalId":344286,"journal":{"name":"IEEE International Electron Devices Meeting 2003","volume":"216 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"A highly manufacturable low power and high speed HfSiO CMOS FET with dual poly-Si gate electrodes\",\"authors\":\"T. Iwamoto, T. Ogura, M. Terai, H. Watanabe, N. Ikarashi, M. Miyamura, T. Tatsumi, M. Saitoh, A. Morioka, K. Watanabe, Y. Saito, Y. Yabe, T. Ikarashi, K. Masuzaki, Y. Mochizuki, T. Mogami\",\"doi\":\"10.1109/IEDM.2003.1269362\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"For 90 nm node poly-Si gated MISFETs with HfSiO (1.8 nm) insulator, a nearly symmetrical set of Vths for NFET and PFET: (0.38 V and -0.46 V, respectively) have been realized for low power device operation. The key technology is the suppression of Vth instability in PFETs arising from oxidation of the poly-Si/HfSiO interface, combined with channel engineering for the PFET. Our poly-Si/HfSiO gate-stacked CMOSFETs realize low I/sub off/ (N/PFET: 4.8/3.6 pA//spl mu/m) and high I/sub on/ (N/PFET: 469/140 /spl mu/A//spl mu/m) at V/sub DD/=1.2 V. Further, for SRAM cell using this CMOS, normal operation has been achieved.\",\"PeriodicalId\":344286,\"journal\":{\"name\":\"IEEE International Electron Devices Meeting 2003\",\"volume\":\"216 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Electron Devices Meeting 2003\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2003.1269362\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Electron Devices Meeting 2003","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2003.1269362","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A highly manufacturable low power and high speed HfSiO CMOS FET with dual poly-Si gate electrodes
For 90 nm node poly-Si gated MISFETs with HfSiO (1.8 nm) insulator, a nearly symmetrical set of Vths for NFET and PFET: (0.38 V and -0.46 V, respectively) have been realized for low power device operation. The key technology is the suppression of Vth instability in PFETs arising from oxidation of the poly-Si/HfSiO interface, combined with channel engineering for the PFET. Our poly-Si/HfSiO gate-stacked CMOSFETs realize low I/sub off/ (N/PFET: 4.8/3.6 pA//spl mu/m) and high I/sub on/ (N/PFET: 469/140 /spl mu/A//spl mu/m) at V/sub DD/=1.2 V. Further, for SRAM cell using this CMOS, normal operation has been achieved.
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