{"title":"新型AES加密算法微电路设计","authors":"K. Volkan Dalmisli, Berna Ors","doi":"10.1109/ICSCS.2009.5414191","DOIUrl":null,"url":null,"abstract":"Advanced Encryption Standard (AES) maintains safety and is used for providing security since publishing date. At the present day, crypto devices are produced in order to be smaller and faster. So, AES chips should not only use very small area, but also have enough throughput. In this paper, we present an 8-bit implementation of the AES algorithm which encrypts plaintext with 14.3 Mbps throughput and lays on 4300 GE on ASIC and 299 slices on FPGA devices. We use only one s-box and a quarter mix column modules as significant points.","PeriodicalId":126072,"journal":{"name":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Design of new tiny circuits for AES encryption algorithm\",\"authors\":\"K. Volkan Dalmisli, Berna Ors\",\"doi\":\"10.1109/ICSCS.2009.5414191\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Advanced Encryption Standard (AES) maintains safety and is used for providing security since publishing date. At the present day, crypto devices are produced in order to be smaller and faster. So, AES chips should not only use very small area, but also have enough throughput. In this paper, we present an 8-bit implementation of the AES algorithm which encrypts plaintext with 14.3 Mbps throughput and lays on 4300 GE on ASIC and 299 slices on FPGA devices. We use only one s-box and a quarter mix column modules as significant points.\",\"PeriodicalId\":126072,\"journal\":{\"name\":\"2009 3rd International Conference on Signals, Circuits and Systems (SCS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 3rd International Conference on Signals, Circuits and Systems (SCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSCS.2009.5414191\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 3rd International Conference on Signals, Circuits and Systems (SCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSCS.2009.5414191","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of new tiny circuits for AES encryption algorithm
Advanced Encryption Standard (AES) maintains safety and is used for providing security since publishing date. At the present day, crypto devices are produced in order to be smaller and faster. So, AES chips should not only use very small area, but also have enough throughput. In this paper, we present an 8-bit implementation of the AES algorithm which encrypts plaintext with 14.3 Mbps throughput and lays on 4300 GE on ASIC and 299 slices on FPGA devices. We use only one s-box and a quarter mix column modules as significant points.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
