三维fpga中的多路开关盒结构，以减少硅面积和提高TSV使用率

ACM Great Lakes Symposium on VLSI Pub Date : 2012-05-03 DOI:10.1145/2206781.2206855

Marzieh Morshedzadeh, A. Jahanian

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引用次数: 2

摘要

在本文中，我们提出了一种多路复用的3d开关盒架构，该架构减少了路由所需的tsv数量，并且总长度上有轻微的开销。我们的实验结果表明，所提出的架构减少了约48%的路由tsv的成本，而带宽开销不到2%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage

In this paper, we propose a multiplexed 3D-switch box architecture that decreases the number of TSVs required for routing with a slight overhead in total wirelength. Our experimental results show that the presented architecture reduces the number of routing TSVs by about 48% in cost of less than 2% wirelength overhead.

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ACM Great Lakes Symposium on VLSI

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