Design and analysis of new energy efficient glitch free adiabatic logic circuit

The interest for ultra-low power integrated circuits in the recent past has guided the research community to establish the proposal of several adiabatic logic circuits in which the energy stored can be efficiently recycled. Many of these architectures suffer from problems like glitch & huge number of transistors as compared to conventional CMOS, which stop them to be used in practical scenario. As a consequence, we tried to come up with a new circuit that could address the above said limitations. In this work, we have proposed a new adiabatic logic where glitches are reduced drastically such that Logic 0 & Logic 1 level looks almost like what we generally have in conventional CMOS circuit output. The new logic is applied to design NOT, NAND & NOR gate as these are the fundamental building blocks of any digital system. The simulation of the circuits is done in 180 nm Technology and a significant savings in power and energy has been achieved after comparing with the conventional CMOS and a few previous well known adiabatic logics.