Reduced current class AB radio receiver stages using novel superlinear transistors with parallel NMOS and PMOS transistors at one GHz

Class AB amplifier stages are commonly used to conserve power in radio transmitters. In this paper, a Class AB amplifier stage is investigated for use in radio receivers to reduce power consumption. In this, a novel superlinear three-terminal transistor consisting of an NMOS transistor in parallel with a PMOS transistor is used to improve Class AB linearity to a level approaching Class A performance. Optimum transistor bias conditions for the linearized Class AB receiver stage are also presented. Measured and simulated results at 1 GHz show supply current reduction of approximately 40 percent and 4 dB improvement in third order intercept point using linearization. Finally, simulations of an improved Class AB design show third order output intercept better than a corresponding Class A stage and show more than 50 percent reduction in power consumption.