基于组合逻辑Sigmoid函数的VHDL多层感知器神经网络结构

S. P. Joy Vasantha Rani, P. Kanagasabapathy
{"title":"基于组合逻辑Sigmoid函数的VHDL多层感知器神经网络结构","authors":"S. P. Joy Vasantha Rani, P. Kanagasabapathy","doi":"10.1109/ICSCN.2007.350771","DOIUrl":null,"url":null,"abstract":"This paper presents the hardware realization of fast and flexible feed forward neural network which is capable of dealing with fixed point arithmetic operations using VHDL with minimum number of CLB slices and good speed of performance. The hardware architecture of neural network with two input, one output and three hidden neurons occupies only 44% of CLB slices. An efficient and fast carry look-ahead adder and Booth multiplier are the essential building blocks of the processing elements to perform parallel computation in the neural network. The activation function has been carried out based on piecewise linear approximation only with combinational logic circuits","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Multilayer Perceptron Neural Network Architecture using VHDL with Combinational Logic Sigmoid Function\",\"authors\":\"S. P. Joy Vasantha Rani, P. Kanagasabapathy\",\"doi\":\"10.1109/ICSCN.2007.350771\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the hardware realization of fast and flexible feed forward neural network which is capable of dealing with fixed point arithmetic operations using VHDL with minimum number of CLB slices and good speed of performance. The hardware architecture of neural network with two input, one output and three hidden neurons occupies only 44% of CLB slices. An efficient and fast carry look-ahead adder and Booth multiplier are the essential building blocks of the processing elements to perform parallel computation in the neural network. The activation function has been carried out based on piecewise linear approximation only with combinational logic circuits\",\"PeriodicalId\":257948,\"journal\":{\"name\":\"2007 International Conference on Signal Processing, Communications and Networking\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 International Conference on Signal Processing, Communications and Networking\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSCN.2007.350771\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Conference on Signal Processing, Communications and Networking","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSCN.2007.350771","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9

摘要

本文提出了一种基于VHDL的快速灵活的前馈神经网络的硬件实现方法,该神经网络具有处理定点算术运算的能力,并且具有最少的CLB切片数和良好的性能速度。两输入一输出、三个隐藏神经元的神经网络硬件结构仅占CLB切片的44%。高效、快速的进位前瞻加法器和布斯乘法器是实现神经网络并行计算的基本组成部分。激活函数仅在组合逻辑电路中基于分段线性逼近实现
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Multilayer Perceptron Neural Network Architecture using VHDL with Combinational Logic Sigmoid Function
This paper presents the hardware realization of fast and flexible feed forward neural network which is capable of dealing with fixed point arithmetic operations using VHDL with minimum number of CLB slices and good speed of performance. The hardware architecture of neural network with two input, one output and three hidden neurons occupies only 44% of CLB slices. An efficient and fast carry look-ahead adder and Booth multiplier are the essential building blocks of the processing elements to perform parallel computation in the neural network. The activation function has been carried out based on piecewise linear approximation only with combinational logic circuits
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