Tara Prasanna Dash, S. Dey, S. Das, E. Mohaptra, J. Jena, C. K. Maiti
{"title":"7nm纳米finfet的应力调谐","authors":"Tara Prasanna Dash, S. Dey, S. Das, E. Mohaptra, J. Jena, C. K. Maiti","doi":"10.1109/EDKCON.2018.8770517","DOIUrl":null,"url":null,"abstract":"In nanoelectronics, the device performance evolution is limited by the down-scaling. Introduction of intentional mechanical stress is a potential mobility booster to overcome these limitations. However, it is essential to properly control the stress during process integration to understand the influence on channel transport. The aim of this work is to study the mechanical stress evolution in a tri-gate FinFET at 7nm technology node using technology CAD (TCAD) simulations. Using stress maps, we analyze the mechanical stress impact on the transfer characteristics of the device. Suitability of TCAD to explore the potential of new innovative strain-engineered device structures for future generations of CMOS technology is demonstrated.","PeriodicalId":344143,"journal":{"name":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Stress Tuning in NanoScale FinFETs at 7nm\",\"authors\":\"Tara Prasanna Dash, S. Dey, S. Das, E. Mohaptra, J. Jena, C. K. Maiti\",\"doi\":\"10.1109/EDKCON.2018.8770517\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In nanoelectronics, the device performance evolution is limited by the down-scaling. Introduction of intentional mechanical stress is a potential mobility booster to overcome these limitations. However, it is essential to properly control the stress during process integration to understand the influence on channel transport. The aim of this work is to study the mechanical stress evolution in a tri-gate FinFET at 7nm technology node using technology CAD (TCAD) simulations. Using stress maps, we analyze the mechanical stress impact on the transfer characteristics of the device. Suitability of TCAD to explore the potential of new innovative strain-engineered device structures for future generations of CMOS technology is demonstrated.\",\"PeriodicalId\":344143,\"journal\":{\"name\":\"2018 IEEE Electron Devices Kolkata Conference (EDKCON)\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE Electron Devices Kolkata Conference (EDKCON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDKCON.2018.8770517\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE Electron Devices Kolkata Conference (EDKCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDKCON.2018.8770517","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In nanoelectronics, the device performance evolution is limited by the down-scaling. Introduction of intentional mechanical stress is a potential mobility booster to overcome these limitations. However, it is essential to properly control the stress during process integration to understand the influence on channel transport. The aim of this work is to study the mechanical stress evolution in a tri-gate FinFET at 7nm technology node using technology CAD (TCAD) simulations. Using stress maps, we analyze the mechanical stress impact on the transfer characteristics of the device. Suitability of TCAD to explore the potential of new innovative strain-engineered device structures for future generations of CMOS technology is demonstrated.
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