{"title":"高性能4:1多路复用器，双极双栅fet","authors":"K. Jabeur, I. O’Connor, N. Yakymets, S. L. Beux","doi":"10.1109/ICECS.2011.6122365","DOIUrl":null,"url":null,"abstract":"In this paper, we exploit the ambipolarity property of double gate devices such as DG-CNTFETs to design a new 4:1 multiplexer, with a significant reduction in circuit complexity with respect to conventional CMOS-based multiplexers for equivalent functionality. Based on Pass-Transistor Logic, it demonstrates performance improvement of up to 3× concerning Power-Delay-Product reduction, as compared to conventional multiplexers, and an area reduction of at least 2× compared to any 4:1 multiplexer, and up to 3× when compared to a static-logic design.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"High performance 4:1 multiplexer with ambipolar double-gate FETs\",\"authors\":\"K. Jabeur, I. O’Connor, N. Yakymets, S. L. Beux\",\"doi\":\"10.1109/ICECS.2011.6122365\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we exploit the ambipolarity property of double gate devices such as DG-CNTFETs to design a new 4:1 multiplexer, with a significant reduction in circuit complexity with respect to conventional CMOS-based multiplexers for equivalent functionality. Based on Pass-Transistor Logic, it demonstrates performance improvement of up to 3× concerning Power-Delay-Product reduction, as compared to conventional multiplexers, and an area reduction of at least 2× compared to any 4:1 multiplexer, and up to 3× when compared to a static-logic design.\",\"PeriodicalId\":251525,\"journal\":{\"name\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2011.6122365\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2011.6122365","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High performance 4:1 multiplexer with ambipolar double-gate FETs
In this paper, we exploit the ambipolarity property of double gate devices such as DG-CNTFETs to design a new 4:1 multiplexer, with a significant reduction in circuit complexity with respect to conventional CMOS-based multiplexers for equivalent functionality. Based on Pass-Transistor Logic, it demonstrates performance improvement of up to 3× concerning Power-Delay-Product reduction, as compared to conventional multiplexers, and an area reduction of at least 2× compared to any 4:1 multiplexer, and up to 3× when compared to a static-logic design.
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