容错路由器，内置自检/自诊断和故障隔离电路，用于基于2d网格的芯片多处理器系统

2009 International Symposium on VLSI Design, Automation and Test Pub Date : 2009-04-28 DOI:10.1109/VDAT.2009.5158098

Shu-Yen Lin, Wen-Chung Shen, Chan-Cheng Hsu, Chih-Hao Chao, A. Wu

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引用次数: 47

摘要

针对基于二维网格的芯片多处理器系统，提出了一种容错路由器设计(20路路由器)，以减少路由器故障对系统的影响。在我们的实验中，与使用通用XY路由器的ocn相比，使用20pr的ocn可以减少75.65% ~ 85.01%的不可达数据包和7.78% ~ 26.59%的延迟。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Fault-tolerant router with built-in self-test/self-diagnosis and fault-isolation circuits for 2D-mesh based chip multiprocessor systems

A fault-tolerant router design (20-path router) is proposed to reduce the impacts of faulty routers for 2D-mesh based chip multiprocessor systems. In our experiments, the OCNs using 20PRs can reduce 75.65% ∼ 85.01% unreachable packets and 7.78% ∼ 26.59% latency in comparison with the OCNs using generic XY routers.

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2009 International Symposium on VLSI Design, Automation and Test

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