{"title":"一种基于电容的D/A转换器,具有连续时间输出,适用于低功耗应用","authors":"L. Lynn, P. Ferguson","doi":"10.1145/263272.263304","DOIUrl":null,"url":null,"abstract":"A digital to analog converter has been developed using switched capacitors as the basic DAC elements. The use of switching capacitors provides excellent matching without sacrificing die area, and allows for very low-power operation. However, the architecture provides significant challenges when used in a continuous-time application requiring a \"smooth\" output. A realization of this architecture in a standard 0.6 /spl mu/m CMOS process achieved 10 bits of linearity while consuming less than 200 /spl mu/A of current.","PeriodicalId":334688,"journal":{"name":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A capacitor-based D/A converter with continuous time output for low-power applications\",\"authors\":\"L. Lynn, P. Ferguson\",\"doi\":\"10.1145/263272.263304\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A digital to analog converter has been developed using switched capacitors as the basic DAC elements. The use of switching capacitors provides excellent matching without sacrificing die area, and allows for very low-power operation. However, the architecture provides significant challenges when used in a continuous-time application requiring a \\\"smooth\\\" output. A realization of this architecture in a standard 0.6 /spl mu/m CMOS process achieved 10 bits of linearity while consuming less than 200 /spl mu/A of current.\",\"PeriodicalId\":334688,\"journal\":{\"name\":\"Proceedings of 1997 International Symposium on Low Power Electronics and Design\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1997 International Symposium on Low Power Electronics and Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/263272.263304\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1997 International Symposium on Low Power Electronics and Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/263272.263304","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A capacitor-based D/A converter with continuous time output for low-power applications
A digital to analog converter has been developed using switched capacitors as the basic DAC elements. The use of switching capacitors provides excellent matching without sacrificing die area, and allows for very low-power operation. However, the architecture provides significant challenges when used in a continuous-time application requiring a "smooth" output. A realization of this architecture in a standard 0.6 /spl mu/m CMOS process achieved 10 bits of linearity while consuming less than 200 /spl mu/A of current.