Area Efficient VLSI Architecture for Reversible Radix-2 FFT Algorithm using Folding Technique and Reversible Gate

FFT is normally utilized in computerized flag preparing algorithms. 4G correspondence and different remote framework based correspondence are directly hotly debated issues of innovative work in the remote correspondence and organizing field. FFT is a calculation that speeds up the count of DFT. In the main stage, low multifaceted nature Radix-2 Multi-way Delay Commutator (R2MDC) FFT recurrence change method is created through Exceptionally Large Scale Integration System structure condition. Low power utilization, less zone and rapid are the VLSI primary parameters. Customary R2MDC FFT structure has more equipment multifaceted nature because of its escalated computational components. Two strategies are utilized to plan radix-2 FFT calculation. In firest strategy is plan radix-2 FFT with the help of reversible Peres gate and TR gate. Second method is design radix-2 FFT with the help of reversible DKG Gate. The all structure are usage vertex-4 gadget family Xilinx programming and looked at past calculation.