Implementation of Efficient Probabilistic Symmetric Key Encryption Method

This paper covers the implementation of efficient probabilistic symmetric key encryption using International Data Encryption Algorithm (IDEA). The current era has seen an explosive growth in communication. Applications like online banking, personal digital assistants, mobile communication, smartcards, etc. have emphasized the need for security in resource constrained environment. International Data Encryption Algorithm (IDEA) cryptography serves as a perfect encryption tool because of its 128 bits key sizes and high security comparable to that of other algorithms. However, to match the ever increasing requirement for speed in today’s applications, hardware acceleration of the cryptographic algorithms is a necessity. This study presents an efficient hardware structure for the modulo (2 n + 1) Multiplier and modulo(2 n ) adder which is the most time and space consuming operation in IDEA. The proposed design saves more time, area and cost. The block size considered here is same as of traditional IDEA encryption algorithm which is of 64 bits with 16 bit sub-blocks.