VLSI design of mixed radix FFT Processor for MIMO OFDM in wireless communications

Orthogonal frequency division multiplexing (OFDM) is a popular method for high data rate wireless transmission. OFDM may be merged with antenna arrays at the transmitter and receiver to increase the diversity gain and/or to heighten the system capacity on time-variant and frequency-selective channels, resulting in a Multiple-Input Multiple-Output (MIMO) configuration. The IEEE 802.11n standard based on the MIMO OFDM system provides a very high data throughput from the original data rate of 54 Mb/s to the data rate in excess of 600 Mb/s, because the technique of the MIMO can increase the data rate by extending an OFDM-based system. However, the IEEE 802.11n standard also increases the computational and the hardware complexities greatly, compared with the current Wireless Local Area Network (WLAN) standards. It is a challenge to realize the physical layer of the MIMO OFDM system with minimal hardware complexity and power consumption especially the computational complexity in VLSI implementation. The Fast Fourier Transform / Inverse Fast Fourier Transform (FFT/IFFT) processor is one of the highest computationally complex modules in the physical layer of the IEEE 802.11n standard. However to improve the signal processing capability and to reduce the power consumption as well as the hardware cost of a FFT processor have become challenging targets. In this paper present a pipelined Fast Fourier Transform (FFT) / Inverse Fast Fourier Transform (IFFT) processor for the applications in a MIMO OFDM based IEEE 802.11n WLAN baseband processor is presented. High throughput, memory reduction, low power and complex multiplier reduction are achieved by using higher mixed radix FFT in MIMO-OFDM. The mixed-radix 4/2 with bit reversal FFT architecture is proposed to design the prototype FFT/IFFT processor for MIMO-OFDM systems. The proposed processor with minimal hardware complexity reduces the power consumption.