一种低内存要求的非均匀网格投影超分辨率算法执行流程

T. Szydzik, G. Callicó, A. Núñez
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引用次数: 1

摘要

在这项工作中,我们提出了一种新的超分辨率图像恢复(SRIR)非均匀网格投影算法的执行流程——宏块级流程。将该流程与参考帧级流程进行了比较。帧级流的特点是,只有对当前正在处理的帧的所有宏块(mb)执行当前步骤之后,才会发生从算法的一个步骤到另一个步骤的转换。新流程在开始处理另一个MB之前完成一个MB的处理。对两种方案的内存需求进行了详细的评估和比较。对滑动帧窗口中包含的MB大小、比例因子、搜索区域大小和参考帧数量等不同的算法参数值,进行了在总内存需求方面可实现的内存缩减研究。结果定量地表明,对存储实例化影响最大、对总内存大小影响最大的参数是滑动帧窗口中的参考帧数。所进行的研究表明,对于QCIF帧格式,从帧级切换到宏块级是可行的,并且在功能上得到了充分验证,并且根据算法参数值的不同,新的执行流程可以使内存减少6.8到40倍。内存减少极大地促进了算法的硬件实现,这是所声称的主要结果。但是内存大小的减小是以增加内存访问次数和通信流量为代价的。内存的增加将在未来的工作中进行量化,并对功耗产生潜在影响。内存大小的减小也可能使其适合芯片而无需转向外部存储器,从而降低功耗。这种权力上的权衡还有待量化。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Low Memory Requirements Execution Flow for the Non-Uniform Grid Projection Super-Resolution Algorithm
In this work we present a novel execution flow for the super-resolution image restoration (SRIR) non-uniform grid projection algorithm -- the macroblock-level flow. The novel flow is compared with the reference frame-level flow. The frame-level flow is characterized by the fact that transitions from one step of the algorithm to another occur only after the current step is carried out for all macro blocks (MBs) of the frame being currently processed. The novel flow carries out complete processing of one MB before the processing of another MB starts. The memory requirements of both schemes are evaluated in detail and compared. The study on the achievable memory reduction in total memory requirements was carried out for different values of the algorithm parameters: the MB size, scale factor, search area size and number of reference frames included in the sliding frame window. The results show quantitatively that the parameter that influences storage instantiation the most and has the greatest influence on the total memory size is the number of reference frames in the sliding frame window. The conducted study shows that, for a QCIF frame format, switching from frame-to macroblock-level is feasible and fully validated functionally and that the new execution flow can lead to memory reduction by a factor of 6.8 to 40, depending on the algorithm parameters values. Memory reduction greatly facilitates hardware implementations of the algorithm and this is the main result claimed. But the reduction in memory size comes at the cost of increasing the number of memory accesses and therefore communications traffic. The increase noted in memory accesses it to be quantified in future work as well as the potential impact on power consumption. The reduction in memory size might also make it fit on chip without turning to external memory, thereby reducing power consumption. This trade off in power is yet to be quantified.
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