基于码相关非线性补偿和段间电流失配校正的12位8GS/s射频采样DAC

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI:10.1109/vlsitechnologyandcir46769.2022.9830442

Byeongwoo Koo, SungHan Do, Sang-Gyu Nam, H. Shin, Sungno Lee, Eunhye Oh, Jaemin Hong, Jungho Lee, Young-Sae Cho, Michael Choi, Jongshin Shin

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引用次数: 1

摘要

本文提出了一种5nm FinFET工艺的12位8GS/s射频采样电流导向DAC。为了最大限度地减少开关驱动器之间的时序差异引起的码相关非线性，提出了时序失配补偿(TMC)架构。对于小尺寸电流单元的高静态线性度，采用绝对DAC (0.0625LSB/代码精度)实现片上电流单元校准方案。该DAC在8GS/s采样频率下功耗为169mW, SFDR为72.2dBc。

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A 12-bit 8GS/s RF Sampling DAC with Code-Dependent Nonlinearity Compensation and Intersegmental Current-Mismatch Calibration in 5nm FinFET

This paper presents a 12-bit 8GS/s RF sampling current-steering DAC in a 5nm FinFET process. To minimize code-dependent nonlinearity caused by the timing differences between switch drivers, the proposed timing mismatch compensation (TMC) architecture is presented. For high static linearity with small size current cell, an on-chip current cell calibration scheme is implemented with absolute DAC (0.0625LSB/code accuracy). The proposed DAC achieves 72.2dBc SFDR, while consuming 169mW at 8GS/s sampling frequency.

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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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