Towards formal verification of cryptographic circuits: A functional approach

Late detection of errors in hardware designs usually results in great costs. On the other hand, the growing advances on this field has let the complexity level to increase extensively. The problem is that the typical Hardware Description Languages (HDL) like VHDL and Verilog are made for synthesis and simulation only. But, the simulation technique could be deficient in complex designs such as the cryptographic circuits. Formal verification has became an important technique towards establishing the correctness of hardware designs. This paper presents a formal verification approach for the cryprographic circuits. It consists on using the functional language Haskell to formally describe both the behavioral and the structural descriptions. In addition, it relies on the use of the hierarchy and modularity techniques in order to reduce the complexity of the designs; and hence simplify the verification task. To show the potential features of the proposed approach, it is applied to the Data Encryption Standard (DES) circuit and its formal specification is presented.