延迟位交错编码调制的LDPC码设计

Yihuan Liao, Lei Yang, Jinhong Yuan, Kechao Huang, Raymond W. K. Leung, Junyi Du
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引用次数: 3

摘要

提出了一种用于延迟位交织编码调制(DBICM)的低密度校验码的设计方法。该方法通过两个级联差分进化(DE)步骤优化码变节点(VN)度分布和不同度VN对DBICM子信道的分配。在每一步中,为了优化VN度分布或信道分配,构造一个奇偶校验矩阵,并为每一代中的每个元素计算相关的解码阈值。在构造每个信道分配的奇偶校验矩阵时,我们提出了一种约束类聚乙二醇编码构造方法。Protograph-EXIT用于计算每个奇偶校验矩阵的解码阈值。我们应用该方法构造了16-QAM DBICM和BICM方案的不规则二进制LDPC码。仿真结果表明,在误码率为10-6的情况下,优化后的LDPC码距离相关容量限制在1 dB以内。此外,LDPC编码的DBICM在码率范围为0.25至0.5时,比BICM对应的信噪比增益为0.5 dB至0.1 dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
LDPC Code Design for Delayed Bit-Interleaved Coded Modulation
This paper proposes a method to design low-density parity-check (LDPC) codes for delayed bit-interleaved coded modulation (DBICM). In the method, the code variable node (VN) degree distributions and the assignments of VNs with different degrees to DBICM subchannels are optimized via two cascaded differential evolution (DE) steps. In each step, to optimize VN degree distribution or channel assignment, a parity-check matrix is constructed, and the associated decoding threshold is calculated for each element in a generation. In constructing a parity-check matrix for each channel assignment, we propose a constraint PEGlike code construction method. Protograph-EXIT is employed to calculate the decoding threshold for each parity-check matrix. We apply the proposed method to construct irregular binary LDPC codes for both 16-QAM DBICM and BICM schemes. Simulation results demonstrate that the optimized LDPC codes are within 1 dB from the associated capacity limit at a bit error rate (BER) of 10–6. Besides, the LDPC coded DBICM achieves an SNR gain of 0.5 dB to 0.1 dB over BICM counterparts at a code rate ranges from 0.25 to 0.5.
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