{"title":"MOS GP计算机","authors":"R. Booher","doi":"10.1145/1476589.1476701","DOIUrl":null,"url":null,"abstract":"When the 2-phase, 20-bit shift registers using P-channel enhancement mode MOS-FET's were first introduced on the market many of us did not have the foggiest idea of what a MOS-FET was. Logical designers were intrigued by the functional complexity which the technology appeared to offer. System designers were pleased with the prospect of lower power and fewer package requirements. Semiconductor manufacturers predicted that MOS would be forgotten sooner than the tunnel diode.","PeriodicalId":294588,"journal":{"name":"Proceedings of the December 9-11, 1968, fall joint computer conference, part I","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1899-12-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"MOS GP computer\",\"authors\":\"R. Booher\",\"doi\":\"10.1145/1476589.1476701\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"When the 2-phase, 20-bit shift registers using P-channel enhancement mode MOS-FET's were first introduced on the market many of us did not have the foggiest idea of what a MOS-FET was. Logical designers were intrigued by the functional complexity which the technology appeared to offer. System designers were pleased with the prospect of lower power and fewer package requirements. Semiconductor manufacturers predicted that MOS would be forgotten sooner than the tunnel diode.\",\"PeriodicalId\":294588,\"journal\":{\"name\":\"Proceedings of the December 9-11, 1968, fall joint computer conference, part I\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1899-12-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the December 9-11, 1968, fall joint computer conference, part I\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1476589.1476701\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the December 9-11, 1968, fall joint computer conference, part I","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1476589.1476701","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
When the 2-phase, 20-bit shift registers using P-channel enhancement mode MOS-FET's were first introduced on the market many of us did not have the foggiest idea of what a MOS-FET was. Logical designers were intrigued by the functional complexity which the technology appeared to offer. System designers were pleased with the prospect of lower power and fewer package requirements. Semiconductor manufacturers predicted that MOS would be forgotten sooner than the tunnel diode.
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