低功耗低噪声CMOS斩波放大器

2010 International Conference on Anti-Counterfeiting, Security and Identification Pub Date : 2010-07-18 DOI:10.1109/ICASID.2010.5551831

Xiao Yang, Jing Yang, Li-fen Lin, Chao-dong Ling

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引用次数: 5

摘要

斩波技术是降低放大器低频偏置和1/f噪声的有效方法。本文设计了一种低功耗、低噪声的CMOS斩波放大器。该斩波放大器由两级放大器组成。斩波放大器的第一级高输出阻抗和第二级等效米勒电容共同构成低通滤波器，滤除调制噪声，因此斩波放大器不需要后置低通滤波器，从而降低了功耗。采用台积电0.18μm CMOS工艺和1.8V电源对斩波放大器电路进行了设计和仿真。仿真结果表明，在100hz时，等效输入噪声为39nV/√Hz，功耗为117μW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Low-power low-noise CMOS chopper amplifier

Chopping technique is an efficient approach to decrease the low-frequency offset and 1/f noise of amplifiers. In this paper, a low-power low-noise CMOS chopper amplifier is designed. This chopper amplifier is composed of a two-stage amplifier. The high output impedance of the first stage and the equivalent Miller capacitance of the second stage amplifier constitute together a low pass filter to filter out the modulation noise, so the chopper amplifier need not the post low-pass filter, which can reduce the power consumption. The circuit of the presented chopper amplifier is designed and simulated with TSMC 0.18μm CMOS process and a 1.8V supply. Simulation results show that the equivalent input noise is 39nV/√Hz at 100 Hz and the power consumption is 117μW.

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2010 International Conference on Anti-Counterfeiting, Security and Identification

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