{"title":"A 20 MHz;CMOS可变增益放大器","authors":"C. Srinivasan, K. Rao","doi":"10.1109/ICVD.1996.489463","DOIUrl":null,"url":null,"abstract":"A variable gain amplifier with a gain range of 15 dB to 4O dB and 80 MHz bandwidth is described here. The circuit is built in a standard CMOS process. A MOS device, operated in the linear region, is used as a shunt feedback element to vary the gain. The circuit embodies an inverse relationship between the gain and the control voltage. The circuit dissipates about 30 mW of power. This circuit has been intended to be used in a PRML read channel chip but can be adapted for other purposes also.","PeriodicalId":301389,"journal":{"name":"Proceedings of 9th International Conference on VLSI Design","volume":"4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 20 MHz; CMOS variable gain amplifier\",\"authors\":\"C. Srinivasan, K. Rao\",\"doi\":\"10.1109/ICVD.1996.489463\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A variable gain amplifier with a gain range of 15 dB to 4O dB and 80 MHz bandwidth is described here. The circuit is built in a standard CMOS process. A MOS device, operated in the linear region, is used as a shunt feedback element to vary the gain. The circuit embodies an inverse relationship between the gain and the control voltage. The circuit dissipates about 30 mW of power. This circuit has been intended to be used in a PRML read channel chip but can be adapted for other purposes also.\",\"PeriodicalId\":301389,\"journal\":{\"name\":\"Proceedings of 9th International Conference on VLSI Design\",\"volume\":\"4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-01-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 9th International Conference on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVD.1996.489463\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 9th International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1996.489463","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A variable gain amplifier with a gain range of 15 dB to 4O dB and 80 MHz bandwidth is described here. The circuit is built in a standard CMOS process. A MOS device, operated in the linear region, is used as a shunt feedback element to vary the gain. The circuit embodies an inverse relationship between the gain and the control voltage. The circuit dissipates about 30 mW of power. This circuit has been intended to be used in a PRML read channel chip but can be adapted for other purposes also.
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