逃离学术沙箱:在赛灵思设备上实现VPR电路

Eddie Hung, F. Eslami, S. Wilton
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引用次数: 49

摘要

本文为FPGA CAD研究人员提供了一种新的、开源的方法,可以在实际的赛灵思器件上实现他们的技术。具体来说,我们扩展了Verilog-To-Routing (VTR)套件,其中包括许多FPGA创新所基于的VPR位置和路由CAD工具,通过Xilinx设计语言(XDL)生成工作的Xilinx比特流。目前,我们可以将VPR的异构封装和放置结果忠实地转换为精确的Xilinx“地图”网表,然后通过其“par”工具进行路由。我们通过针对40nm Virtex-6器件的两个引人注目的应用展示了这种新方法的实用性:学术界最先进的VTR How与商业闭源等效器件的面积、延迟和CAD运行时间的公平比较,以及使用芯片上功耗和芯片温度随时间的物理测量进行CAD实验评估。这个扩展的How - VTR-to-Bitstream -被发布给社区,希望它可以增强现有的研究项目,并解锁新的项目。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices
This paper presents a new, open-source method for FPGA CAD researchers to realize their techniques on real Xilinx devices. Specifically, we extend the Verilog-To-Routing (VTR) suite, which includes the VPR place-and-route CAD tool on which many FPGA innovations have been based, to generate working Xilinx bitstreams via the Xilinx Design Language (XDL). Currently, we can faithfully translate VPR's heterogeneous packing and placement results into an exact Xilinx `map' netlist, which is then routed by its `par' tool. We showcase the utility of this new method with two compelling applications targeting a 40nm Virtex-6 device: a fair comparison of the area, delay, and CAD runtime of academia's state-of-the-art VTR How with a commercial, closed-source equivalent, along with a CAD experiment evaluated using physical measurements of on-chip power consumption and die temperature, over time. This extended How - VTR-to-Bitstream - is released to the community with the hope that it can enhance existing research projects as well as unlock new ones.
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