An Energy-Efficient Full-Adder Design Using Pass-Transistor Logic

Recently, the data processing capability of the electronic chip is increased significantly. In general data processing means the arithmetic operation on that data. As a result, we have seen that the ALU is present in any data processor. So, the full adder becomes an essential part of the logical and arithmetic unit of the processor. To improve the computational performance of the chip, the improvement of a full adder is necessary. An appropriate logic style helps the designer to design an efficient full adder. In this paper, several logic styles are briefly discussed. We choose to pass transistor logic style to design our new full adder. This logic style is used for reducing power consumption and increasing operational speed. The proposed adder consists of 10 transistors. LTSPICE simulator is used for simulating the schematic. 16nm low power high-k strained silicon transistor model is used for achieving design objectives. A practical transistor model is employed to encounter all practical aspects. The overall performance of the proposed adder circuit is analyzed and compared with conventional circuits.