L. Kang, Jay Kim, JK Lee, WS Shin, N. Kim, SY Park
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Pattern process is a main process to fabricate redistribution layer on carrier and all process has been developed and proven with reliability tests. The fabricated redistribution layer has been developed with low Dk/Df dielectric materials. In order to validate, EVT(Engineering Validation Test) vehicle has been designed. nSiP module size which includes Components with 3-die and 65-passvie is $10\\times 10\\ \\ \\text{mm}$ with thickness 1 mm. The fabricated redistribution layer consists of 4-metal and 4-passivation layers in daisy chain format for reliability test nSiP platform technology can reduce overall module size down to 31% compared to conventional system in package technology. EMI shielding structure has been developed. Panel Level Package technology will add further benefit of cost competitiveness. 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引用次数: 1
摘要
nSiP(nepes System in Package)平台技术已被开发并验证为一个模块概念的SiP封装,该封装可以包含多种芯片和多种无源,通过使用WLP和扇出相关技术用于各种应用。nSiP平台技术已被证明可以减少金属布线层的堆叠,因为它具有精细的5/ 5um线路和空间能力,并提高了电气性能。nSiP平台技术是一种基于双面基板技术、高密度双面贴装技术、嵌入式走线基板甚至无需传统PCB基板技术的基本结构。nSiP模组的制程包括图案制程、表面贴装(SMT)和封装(& B/E)。图案工艺是在载体上制作重分布层的主要工艺,所有工艺都经过了可靠性试验的验证。用低Dk/Df介电材料制备了重分布层。为了验证,设计了EVT(工程验证试验)车辆。nSiP模块的尺寸(包括3-die和65- pasvie组件)为$10\ × 10\ \ \text{mm}$,厚度为1 mm。制造的再分配层由4-金属层和4-钝化层组成,采用菊花链格式,用于可靠性测试。与传统的系统封装技术相比,nSiP平台技术可以将整体模块尺寸减小到31%。研制了电磁干扰屏蔽结构。面板级封装技术将进一步增加成本竞争力。由于每个客户都有自己的SiP需求,nSiP平台技术可以作为任何应用和任何结构的SiP模块解决方案,可以包含任何功能,如3D PoP,双面SiP, 5G毫米波封装解决方案等。
nSiP(System in Package) Platform for various module packaging applications
nSiP(nepes System in Package) platform technology has been developed and verified as a module concept SiP package which can contain various dies and multi passives by using WLP and fan-out related technologies for various applications. nSiP platform technology has been proven to be enabling less stack up of metal routing layers due to fine 5/5 um line and spaces capabilities and improving the electrical performance. nSiP platform technology is a basic structure based on the fabricated redistribution layer for double side substrate technology, high density and double side mount technology, embedded trace substrate even without conventional PCB substrate technology. The process of nSiP module consists of Pattern process, Surface mounting (SMT) and Encapsulation (& B/E). Pattern process is a main process to fabricate redistribution layer on carrier and all process has been developed and proven with reliability tests. The fabricated redistribution layer has been developed with low Dk/Df dielectric materials. In order to validate, EVT(Engineering Validation Test) vehicle has been designed. nSiP module size which includes Components with 3-die and 65-passvie is $10\times 10\ \ \text{mm}$ with thickness 1 mm. The fabricated redistribution layer consists of 4-metal and 4-passivation layers in daisy chain format for reliability test nSiP platform technology can reduce overall module size down to 31% compared to conventional system in package technology. EMI shielding structure has been developed. Panel Level Package technology will add further benefit of cost competitiveness. Since each customer has their own SiP requirement, nSiP platform technology can be a solution as SiP module for any applications and any structures which can include any functions, like 3D PoP, double side SiP, 5G mmWave package solution and so on.