基于ldo的电源参考10b 32MS/s流水线ADC

Chang-Kyo Lee, Ji-Wook Kwon, Sang-Hyun Cho, S. Ryu
{"title":"基于ldo的电源参考10b 32MS/s流水线ADC","authors":"Chang-Kyo Lee, Ji-Wook Kwon, Sang-Hyun Cho, S. Ryu","doi":"10.1109/IMWS2.2011.6027169","DOIUrl":null,"url":null,"abstract":"A reference driver-free pipelined ADC with a low drop-out (LDO) regulator for power supply is proposed for SoC applications. An LDO-based regulated voltage provides not only power supply for digital and analog circuits but also works as a reference voltage for the ADC. Conventional residue function from a 2.5b/stage design can use its max input as much as 93% of the internal supply voltage. A prototype 10-bit 32MS/s ADC has been designed for a 0.18µm CMOS technology. Under a regulated 1.5V internal supply from an external 1.8V, the design shows 65.1dB SFDR with 7.06mA (including LDO) current consumption.","PeriodicalId":367154,"journal":{"name":"2011 IEEE MTT-S International Microwave Workshop Series on Intelligent Radio for Future Personal Terminals","volume":"659 ","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An LDO-based supply referencing 10b 32MS/s pipelined ADC\",\"authors\":\"Chang-Kyo Lee, Ji-Wook Kwon, Sang-Hyun Cho, S. Ryu\",\"doi\":\"10.1109/IMWS2.2011.6027169\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A reference driver-free pipelined ADC with a low drop-out (LDO) regulator for power supply is proposed for SoC applications. An LDO-based regulated voltage provides not only power supply for digital and analog circuits but also works as a reference voltage for the ADC. Conventional residue function from a 2.5b/stage design can use its max input as much as 93% of the internal supply voltage. A prototype 10-bit 32MS/s ADC has been designed for a 0.18µm CMOS technology. Under a regulated 1.5V internal supply from an external 1.8V, the design shows 65.1dB SFDR with 7.06mA (including LDO) current consumption.\",\"PeriodicalId\":367154,\"journal\":{\"name\":\"2011 IEEE MTT-S International Microwave Workshop Series on Intelligent Radio for Future Personal Terminals\",\"volume\":\"659 \",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-09-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE MTT-S International Microwave Workshop Series on Intelligent Radio for Future Personal Terminals\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMWS2.2011.6027169\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE MTT-S International Microwave Workshop Series on Intelligent Radio for Future Personal Terminals","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMWS2.2011.6027169","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

提出了一种用于SoC应用的参考无驱动器流水线ADC,具有低差(LDO)稳压器。基于ldo的稳压电压不仅可以为数字和模拟电路提供电源,还可以作为ADC的参考电压。2.5b/级设计的常规剩余函数可以使用其最大输入高达内部电源电压的93%。基于0.18µm CMOS技术设计了一个10位32MS/s原型ADC。在外部1.8V稳压1.5V内部电源下,该设计显示出65.1dB SFDR和7.06mA(包括LDO)电流消耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An LDO-based supply referencing 10b 32MS/s pipelined ADC
A reference driver-free pipelined ADC with a low drop-out (LDO) regulator for power supply is proposed for SoC applications. An LDO-based regulated voltage provides not only power supply for digital and analog circuits but also works as a reference voltage for the ADC. Conventional residue function from a 2.5b/stage design can use its max input as much as 93% of the internal supply voltage. A prototype 10-bit 32MS/s ADC has been designed for a 0.18µm CMOS technology. Under a regulated 1.5V internal supply from an external 1.8V, the design shows 65.1dB SFDR with 7.06mA (including LDO) current consumption.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信