{"title":"用于多芯电池组的锂离子电池管理芯片","authors":"Yidie Ye, Chen Chen, Jin Jin, Lenian He","doi":"10.1109/APCCAS.2008.4746078","DOIUrl":null,"url":null,"abstract":"This paper introduces a method of realizing a monolithic battery management chip for a lithium ion battery pack of multi-cell in series. High precision subtractor amplifiers were employed to extract the voltage information of each battery. With the utilization of the subtractor amplifiers, the whole system was allowed to be implemented in a normal, nonexpensive standard CMOS process with 5 V supply voltage, instead of a costly high-voltage process. A testing chip was implemented by using CSMCpsilas 0.5 mum 5 V N-well CMOS process. The chip was designed for double-cell battery pack and compatible with single-cell application. The testing results showed this chip functioned well in both applications of double-cell and single-cell, and revealed that the present design method would be suitable for the multi-cell battery packs.","PeriodicalId":344917,"journal":{"name":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Li-ion battery management chip for multi-cell battery pack\",\"authors\":\"Yidie Ye, Chen Chen, Jin Jin, Lenian He\",\"doi\":\"10.1109/APCCAS.2008.4746078\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces a method of realizing a monolithic battery management chip for a lithium ion battery pack of multi-cell in series. High precision subtractor amplifiers were employed to extract the voltage information of each battery. With the utilization of the subtractor amplifiers, the whole system was allowed to be implemented in a normal, nonexpensive standard CMOS process with 5 V supply voltage, instead of a costly high-voltage process. A testing chip was implemented by using CSMCpsilas 0.5 mum 5 V N-well CMOS process. The chip was designed for double-cell battery pack and compatible with single-cell application. The testing results showed this chip functioned well in both applications of double-cell and single-cell, and revealed that the present design method would be suitable for the multi-cell battery packs.\",\"PeriodicalId\":344917,\"journal\":{\"name\":\"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APCCAS.2008.4746078\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APCCAS.2008.4746078","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
介绍了一种多芯串联锂离子电池组单片电池管理芯片的实现方法。采用高精度减法放大器提取每个电池的电压信息。随着减法放大器的使用,整个系统可以在一个正常的、不昂贵的标准CMOS工艺中实现,电源电压为5 V,而不是昂贵的高压工艺。采用CSMCpsilas 0.5 μ m 5 V n阱工艺制作了测试芯片。该芯片专为双芯电池组设计,兼容单芯应用。测试结果表明,该芯片在双电池和单电池的应用中都具有良好的性能,并表明该设计方法适用于多电池包。
Li-ion battery management chip for multi-cell battery pack
This paper introduces a method of realizing a monolithic battery management chip for a lithium ion battery pack of multi-cell in series. High precision subtractor amplifiers were employed to extract the voltage information of each battery. With the utilization of the subtractor amplifiers, the whole system was allowed to be implemented in a normal, nonexpensive standard CMOS process with 5 V supply voltage, instead of a costly high-voltage process. A testing chip was implemented by using CSMCpsilas 0.5 mum 5 V N-well CMOS process. The chip was designed for double-cell battery pack and compatible with single-cell application. The testing results showed this chip functioned well in both applications of double-cell and single-cell, and revealed that the present design method would be suitable for the multi-cell battery packs.