用于65nm CMOS的HDTV解码器LSI的速率可控近无损数据压缩IP

2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI:10.1109/ASSCC.2009.5357148

M. Uchiyama, Kohei Oikawa, Naoto Date, Shin-ichiro Koto

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引用次数: 7

摘要

提出了一种速率可控的近无损嵌入式压缩算法“TLS-1”。该算法通过变长编码和定长编码的巧妙结合，保证了选定的压缩比。在CR = 2时，图像质量接近无损。我们将该算法应用于高清电视解码器LSI中的IP，以减少所需的外部存储器容量和带宽。该LSI采用65nm CMOS技术制造。

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A rate-controllable near-lossless data compression IP for HDTV decoder LSI in 65nm CMOS

We propose a rate-controllable near-lossless embedded compression algorithm "TLS-1". The algorithm guarantees a selected compression ratio with the smart combination of variable length coding and fixed length coding. It achieves near-lossless image quality under CR = 2. We apply the algorithm to an IP in an HDTV decoder LSI in order to reduce the required external memory capacity and its bandwidth. The LSI is fabricated in a 65nm CMOS technology.

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2009 IEEE Asian Solid-State Circuits Conference

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