{"title":"采用低频增益和高频升压联合自适应方法的CMOS 3.5 Gbps连续自适应电缆均衡器","authors":"J. Choi, Moon-Sang Hwang, D. Jeong","doi":"10.1109/VLSIC.2003.1221174","DOIUrl":null,"url":null,"abstract":"This paper describes a high-speed CMOS adaptive cable equalizer with the joint adaptation method of low-frequency gain and high-frequency boosting. The adaptation method compares not only the high-frequency contents but also the low-frequency contents. By this joint adaptation method, the adaptation inaccuracy due to amplitude deviation can be reduced. The filter cell in the equalizer uses the variable-capacitor tuning and feed-forward common-mode-voltage biasing technique to achieve high bandwidth. The prototype chip is fabricated in a 0.18 /spl mu/m mixed-mode CMOS process. The realized active area is 0.48 mm/spl times/0.73 mm. The filter cell operates up to 5 Gbps and the adaptive equalizer operates up to 3.5 Gbps over a 15-m RG-58 coaxial cable with a 1.8 V supply and 80 mW power dissipation.","PeriodicalId":270304,"journal":{"name":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"A CMOS 3.5 Gbps continuous-time adaptive cable equalizer with joint adaptation method of low-frequency gain and high-frequency boosting\",\"authors\":\"J. Choi, Moon-Sang Hwang, D. Jeong\",\"doi\":\"10.1109/VLSIC.2003.1221174\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a high-speed CMOS adaptive cable equalizer with the joint adaptation method of low-frequency gain and high-frequency boosting. The adaptation method compares not only the high-frequency contents but also the low-frequency contents. By this joint adaptation method, the adaptation inaccuracy due to amplitude deviation can be reduced. The filter cell in the equalizer uses the variable-capacitor tuning and feed-forward common-mode-voltage biasing technique to achieve high bandwidth. The prototype chip is fabricated in a 0.18 /spl mu/m mixed-mode CMOS process. The realized active area is 0.48 mm/spl times/0.73 mm. The filter cell operates up to 5 Gbps and the adaptive equalizer operates up to 3.5 Gbps over a 15-m RG-58 coaxial cable with a 1.8 V supply and 80 mW power dissipation.\",\"PeriodicalId\":270304,\"journal\":{\"name\":\"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2003.1221174\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2003.1221174","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A CMOS 3.5 Gbps continuous-time adaptive cable equalizer with joint adaptation method of low-frequency gain and high-frequency boosting
This paper describes a high-speed CMOS adaptive cable equalizer with the joint adaptation method of low-frequency gain and high-frequency boosting. The adaptation method compares not only the high-frequency contents but also the low-frequency contents. By this joint adaptation method, the adaptation inaccuracy due to amplitude deviation can be reduced. The filter cell in the equalizer uses the variable-capacitor tuning and feed-forward common-mode-voltage biasing technique to achieve high bandwidth. The prototype chip is fabricated in a 0.18 /spl mu/m mixed-mode CMOS process. The realized active area is 0.48 mm/spl times/0.73 mm. The filter cell operates up to 5 Gbps and the adaptive equalizer operates up to 3.5 Gbps over a 15-m RG-58 coaxial cable with a 1.8 V supply and 80 mW power dissipation.