Area-time optimal digital BiCMOS carry look-ahead adder

Previous research in VLSI adders has identified the existence of tradeoffs between asymptotic area and asymptotic time. This paper presents a systematic method of implementing a BiCMOS carry look-ahead adder design which is optimized with respect to area and time. Since the adder circuits usually lie on the critical path delay of carry generator due to large fan-out and output capacitances, speed determines the clock cycle time. In view of the driving capability of bipolar transistors, the BiCMOS buffer/driver and BiCMOS cells are chosen and modified to drive large fan-out or heavy capacitive loads. Combining the bipolar and CMOS circuits on a single chip, the performance of the carry generator circuit is improved due to the acceleration of the critical path. A comparison between BiCMOS and CMOS parallel adders is made. It is shown that the parallel adders designed using the BiCMOS cells achieved improvement in the performance, by shortening the critical path delay by 32.486% in the case of 16-bit, 58.365% in the case of 32-bit and 79.944% in the case of 66-bit where the delay is calculated as the average propagation delay measured from HSPICE simulations.