基于sram的用户可重新编程门阵列的开发系统

Third Annual IEEE Proceedings on ASIC Seminar and Exhibit Pub Date : 1990-09-17 DOI:10.1109/ASIC.1990.186105

Y. Shibata, H. Funatsu, Y. Ishida, J. Yoshida

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引用次数: 1

摘要

该工具适用于基于sram的基于逻辑块互连架构的用户可重编程门阵列。一种算法导致了一个强大的设计编辑器，其中包含专门用于该器件结构的原理图条目。它自动或手动地确定每个块中的分钟逻辑和布线路径。整个系统通过一般原理图条目和功能描述条目支持分层设计。

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A development system for an SRAM-based user-reprogrammable gate array

This tool is applicable to an SRAM-based user-reprogrammable gate array based on a logic block interconnect architecture. An algorithm which led to a powerful design editor with a schematic entry dedicated to this device structure has been developed. It determines minute logics in each block and wiring paths, both automatically and manually. The total system supports hierarchical designs by general schematic entries and functional description entries.<>

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Third Annual IEEE Proceedings on ASIC Seminar and Exhibit

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