{"title":"基于可重构神经突触可塑性的随机深度神经网络计算","authors":"Zihan Xia, Ya Dong, Jienan Chen, Rui Wan, Shuai Li, Tingyong Wu","doi":"10.1109/SiPS52927.2021.00048","DOIUrl":null,"url":null,"abstract":"With the increasing popularity of deep neural networks (DNNs), a large amount of research effort has been devoted to the hardware acceleration of DNNs to achieve efficient processing. Nevertheless, few works have explored the similarities between the biological essence of DNNs and arithmetic circuits. Moreover, stochastic computing (SC), which implements complex arithmetic operations with simple logic gates, has been applied to the acceleration of DNNs. However, traditional SC suffers from high latency and large hardware cost of pseudo-random number generators (PRNGs). Inspired by neural synaptic plasticity and SC, in this work, we present the reconfigurable neural synaptic plasticity-based computing (RNSP) to mimic the biological neuron behaviors and exploit the parallelism of SC to the full extent while maintaining a small hardware footprint compared to fixed-point counterparts. RNSP converts fixed-point numbers to parallel bits without logic resources, which are then synthesized by bit-wise multiplications and some full adders. In addition, we propose the arithmetic unit based on RNSP and use re-training to mitigate the accuracy degradation. Finally, a convolution engine (CE) built on RNSP with high memory bandwidth efficiency is designed. According to the implementation results on FPGA, the proposed RNSP-based CE outperforms the fixed-point counterpart in terms of power consumption and area.","PeriodicalId":103894,"journal":{"name":"2021 IEEE Workshop on Signal Processing Systems (SiPS)","volume":"7 2-3","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Reconfigurable Neural Synaptic Plasticity-Based Stochastic Deep Neural Network Computing\",\"authors\":\"Zihan Xia, Ya Dong, Jienan Chen, Rui Wan, Shuai Li, Tingyong Wu\",\"doi\":\"10.1109/SiPS52927.2021.00048\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With the increasing popularity of deep neural networks (DNNs), a large amount of research effort has been devoted to the hardware acceleration of DNNs to achieve efficient processing. Nevertheless, few works have explored the similarities between the biological essence of DNNs and arithmetic circuits. Moreover, stochastic computing (SC), which implements complex arithmetic operations with simple logic gates, has been applied to the acceleration of DNNs. However, traditional SC suffers from high latency and large hardware cost of pseudo-random number generators (PRNGs). Inspired by neural synaptic plasticity and SC, in this work, we present the reconfigurable neural synaptic plasticity-based computing (RNSP) to mimic the biological neuron behaviors and exploit the parallelism of SC to the full extent while maintaining a small hardware footprint compared to fixed-point counterparts. RNSP converts fixed-point numbers to parallel bits without logic resources, which are then synthesized by bit-wise multiplications and some full adders. In addition, we propose the arithmetic unit based on RNSP and use re-training to mitigate the accuracy degradation. Finally, a convolution engine (CE) built on RNSP with high memory bandwidth efficiency is designed. According to the implementation results on FPGA, the proposed RNSP-based CE outperforms the fixed-point counterpart in terms of power consumption and area.\",\"PeriodicalId\":103894,\"journal\":{\"name\":\"2021 IEEE Workshop on Signal Processing Systems (SiPS)\",\"volume\":\"7 2-3\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE Workshop on Signal Processing Systems (SiPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SiPS52927.2021.00048\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE Workshop on Signal Processing Systems (SiPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SiPS52927.2021.00048","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reconfigurable Neural Synaptic Plasticity-Based Stochastic Deep Neural Network Computing
With the increasing popularity of deep neural networks (DNNs), a large amount of research effort has been devoted to the hardware acceleration of DNNs to achieve efficient processing. Nevertheless, few works have explored the similarities between the biological essence of DNNs and arithmetic circuits. Moreover, stochastic computing (SC), which implements complex arithmetic operations with simple logic gates, has been applied to the acceleration of DNNs. However, traditional SC suffers from high latency and large hardware cost of pseudo-random number generators (PRNGs). Inspired by neural synaptic plasticity and SC, in this work, we present the reconfigurable neural synaptic plasticity-based computing (RNSP) to mimic the biological neuron behaviors and exploit the parallelism of SC to the full extent while maintaining a small hardware footprint compared to fixed-point counterparts. RNSP converts fixed-point numbers to parallel bits without logic resources, which are then synthesized by bit-wise multiplications and some full adders. In addition, we propose the arithmetic unit based on RNSP and use re-training to mitigate the accuracy degradation. Finally, a convolution engine (CE) built on RNSP with high memory bandwidth efficiency is designed. According to the implementation results on FPGA, the proposed RNSP-based CE outperforms the fixed-point counterpart in terms of power consumption and area.