4位乘法器的ASIC实现

Pravinkumar G. Parate, P. Patil, S. Subbaraman
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引用次数: 17

摘要

近年来,一些基于可编程逻辑的实验系统被设计和实现,这些系统采用硬件设计方法进行编程。软件环境的一个必要组件将是一个标准宏单元库,该库对应于常用的算术和逻辑运算。本文针对可编程逻辑设计了阵列乘法器。这个倍增器是蜂窝的,高度流水线的,只使用本地互连。在本文的后半部分,还介绍了布斯乘法器和华莱士树乘法器,这是乘法器的约简技术之一。该设计特别适用于4位乘法器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
ASIC Implementation of 4 Bit Multipliers
Recently, several experimental systems based on programmable logic have been designed and implemented which are programmed using a hardware design methodology. One necessary component of the software environment will be a library of standard macrocells corresponding to commonly used arithmetic and logical operations. In this paper Array multiplier is designed specially for programmable logic. This multiplier is cellular, highly pipelined and uses only of local interconnections. In the later part of this paper exposure to Booth multiplier and Wallace tree multiplier also has been given which is one of the reduction techniques for multipliers. The design is particularly carried out for a 4-bit multiplier.
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