{"title":"考虑焊线电阻后负载调节稳定的低差稳压器补偿电路","authors":"S. Heng, C. Pham","doi":"10.1109/ECCTD.2007.4529551","DOIUrl":null,"url":null,"abstract":"A compensation circuit which considered a resistance of a bonding wire for improving a load regulation of a low dropout regulator (LDO) is presented. The circuit is designed a conventional 0.18 mu CMOS process that provides a high performance of a load regulation for a LDO despite of a high load current and a high bonding wire resistance. The proposed circuit is not affected by an input to the LDO and an output voltage setting as well as a variation of temperature and threshold voltages of transistors. The output voltage of the LDO which can be maintained at 0.5% fluctuation when a load current change from 0[mA] to 300[mA] is confirmed by simulation results of HSPICE. This characteristic plays an importance role for the design of LDOs at low output voltage with a high output current.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"56 7-8","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Compensated circuit for Low Dropout Regulator having stable load regulation after consideration of bonding wire resistance\",\"authors\":\"S. Heng, C. Pham\",\"doi\":\"10.1109/ECCTD.2007.4529551\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A compensation circuit which considered a resistance of a bonding wire for improving a load regulation of a low dropout regulator (LDO) is presented. The circuit is designed a conventional 0.18 mu CMOS process that provides a high performance of a load regulation for a LDO despite of a high load current and a high bonding wire resistance. The proposed circuit is not affected by an input to the LDO and an output voltage setting as well as a variation of temperature and threshold voltages of transistors. The output voltage of the LDO which can be maintained at 0.5% fluctuation when a load current change from 0[mA] to 300[mA] is confirmed by simulation results of HSPICE. This characteristic plays an importance role for the design of LDOs at low output voltage with a high output current.\",\"PeriodicalId\":445822,\"journal\":{\"name\":\"2007 18th European Conference on Circuit Theory and Design\",\"volume\":\"56 7-8\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 18th European Conference on Circuit Theory and Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECCTD.2007.4529551\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 18th European Conference on Circuit Theory and Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD.2007.4529551","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Compensated circuit for Low Dropout Regulator having stable load regulation after consideration of bonding wire resistance
A compensation circuit which considered a resistance of a bonding wire for improving a load regulation of a low dropout regulator (LDO) is presented. The circuit is designed a conventional 0.18 mu CMOS process that provides a high performance of a load regulation for a LDO despite of a high load current and a high bonding wire resistance. The proposed circuit is not affected by an input to the LDO and an output voltage setting as well as a variation of temperature and threshold voltages of transistors. The output voltage of the LDO which can be maintained at 0.5% fluctuation when a load current change from 0[mA] to 300[mA] is confirmed by simulation results of HSPICE. This characteristic plays an importance role for the design of LDOs at low output voltage with a high output current.