CNTFET SRAM cell with tolerance to removed metallic CNTs

A metallic CNT renders a short circuit between drain and source in a CNTFET. Technologies capable of removing metallic CNTs create open circuits which degrades SRAM cell performance and functionality. In this paper we present a design approach to tolerate removed metallic CNT in CNTFET SRAM. The proposed approach uses an M×N array of uncorrelated CNTs to form a CNTFET. An extremely high probability of having a functional memory array can be obtained with a modest semiconducting CNT probability (Psemi) of 90% and a 1×4 uncorrelated CNT array. Three optimization schemes are also proposed to minimize the impact of metallic CNT removal.